Gaming AMD vs Intel

[Guest]

I read the following article

http://tinyurl.com/8s2aa
on amdzone.com.



Extremetech looks at gameplay experience comparing AMD and Intel CPUs.
I'm surprised they used DDR2 533, but then of course if they were on
the real ball they would be using faster than DDR400 using the Lanparty
board with that 3500+.
The results speak for themselves. The average frame rate across all six
games for the Athlon 64 system is 61fps, while the Pentium 4 averaged
54fps. That's a 13% difference-not tiny, but not large enough to bowl
us over. What is more important, we feel, is how often a game runs
slowly enough that you can feel it. This methodology is consistent with
the one used by a new performance analysis tool in the works at Intel.
We picked arbitrary performance thresholds, but these are numbers based
on years of game playing experience. We picked frame rates at which you
actually notice an impact on how the game feels, not the absolute
minimum required to play and enjoy a game. This is where the Athlon 64
really kicks the Pentium 4 in the teeth. Our P4 system spent almost a
third of the time, across all games, beneath our target minimum FPS.
The Athlon 64 system, on the other hand, spent only 14% of its time
there. This is a difference of a whopping 121%!



"


So I am wanting to get a new system later this fall. I have read other
reviews saying Intel is the way to go for gaming.

I am looking for the best performance in games and for burning dvds/cds
and web browsing. But the high intensity graphics will be from games
like Doom 3.

I don't want a system that will choke on the graphics. I was thiking
about the nvidia latest pci-e card.

Any thoughts on intel vs AMD?

[Derek Baker]

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...I read the following article http://tinyurl.com/8s2aa on amdzone.com.


[QUOTE] So I am wanting to get a new system later this fall. I have read other reviews saying Intel is the way to go for gaming.

What reviews?
I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3. I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?

Yes, AMD all the way.
--
Derek

[McGrandpa]

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...I read the following article http://tinyurl.com/8s2aa on amdzone.com. Extremetech looks at gameplay experience comparing AMD and Intel CPUs. I'm surprised they used DDR2 533, but then of course if they were on the real ball they would be using faster than DDR400 using the Lanparty board with that 3500+. The results speak for themselves. The average frame rate across all six games for the Athlon 64 system is 61fps, while the Pentium 4 averaged 54fps. That's a 13% difference-not tiny, but not large enough to bowl us over. What is more important, we feel, is how often a game runs slowly enough that you can feel it. This methodology is consistent with the one used by a new performance analysis tool in the works at Intel. We picked arbitrary performance thresholds, but these are numbers based on years of game playing experience. We picked frame rates at which you actually notice an impact on how the game feels, not the absolute minimum required to play and enjoy a game. This is where the Athlon 64 really kicks the Pentium 4 in the teeth. Our P4 system spent almost a third of the time, across all games, beneath our target minimum FPS. The Athlon 64 system, on the other hand, spent only 14% of its time there. This is a difference of a whopping 121%! " So I am wanting to get a new system later this fall. I have read other reviews saying Intel is the way to go for gaming. I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3. I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?

Yep, just tell the devs and hardware makers to come up with some 64 bit code
now :)
McG.

[tod]

You would be happy with AMD or Intel, both would play games just fine.
I personal would go AMD as the price for performance is cheaper with AMD.
AMD also beat Intel to coming out with 64 bit CPUs

Rumors are that the new ATI coming out soon is faster then NVIDIA

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...I read the following article http://tinyurl.com/8s2aa on amdzone.com. Extremetech looks at gameplay experience comparing AMD and Intel CPUs. I'm surprised they used DDR2 533, but then of course if they were on the real ball they would be using faster than DDR400 using the Lanparty board with that 3500+. The results speak for themselves. The average frame rate across all six games for the Athlon 64 system is 61fps, while the Pentium 4 averaged 54fps. That's a 13% difference-not tiny, but not large enough to bowl us over. What is more important, we feel, is how often a game runs slowly enough that you can feel it. This methodology is consistent with the one used by a new performance analysis tool in the works at Intel. We picked arbitrary performance thresholds, but these are numbers based on years of game playing experience. We picked frame rates at which you actually notice an impact on how the game feels, not the absolute minimum required to play and enjoy a game. This is where the Athlon 64 really kicks the Pentium 4 in the teeth. Our P4 system spent almost a third of the time, across all games, beneath our target minimum FPS. The Athlon 64 system, on the other hand, spent only 14% of its time there. This is a difference of a whopping 121%! " So I am wanting to get a new system later this fall. I have read other reviews saying Intel is the way to go for gaming. I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3. I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?

[mikey]

AMD is more than just cheaper,they are significantly faster in gameplay,run
much cooler,and were the first with dual core,which could take away the one
edge Intel had in multi-tasking.
As for ATI,they better get a move on if they want to keep pace with
Nvidia,so far all I've heard from them is rumors.They've been promising
Crossfire for months,while Nvidia's SLI has already been here for months,and
the 7800 series gets faster with each new version released.
"tod" <no_spam_i@earthlink.net> wrote in message
news:1FKSe.5326$4P5.4248@newsread2.news.pas.earthlink.net... You would be happy with AMD or Intel, both would play games just fine. I personal would go AMD as the price for performance is cheaper with AMD. AMD also beat Intel to coming out with 64 bit CPUs Rumors are that the new ATI coming out soon is faster then NVIDIA <Conservative.Nate@gmail.com> wrote in message news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...I read the following article http://tinyurl.com/8s2aa on amdzone.com. Extremetech looks at gameplay experience comparing AMD and Intel CPUs. I'm surprised they used DDR2 533, but then of course if they were on the real ball they would be using faster than DDR400 using the Lanparty board with that 3500+. The results speak for themselves. The average frame rate across all six games for the Athlon 64 system is 61fps, while the Pentium 4 averaged 54fps. That's a 13% difference-not tiny, but not large enough to bowl us over. What is more important, we feel, is how often a game runs slowly enough that you can feel it. This methodology is consistent with the one used by a new performance analysis tool in the works at Intel. We picked arbitrary performance thresholds, but these are numbers based on years of game playing experience. We picked frame rates at which you actually notice an impact on how the game feels, not the absolute minimum required to play and enjoy a game. This is where the Athlon 64 really kicks the Pentium 4 in the teeth. Our P4 system spent almost a third of the time, across all games, beneath our target minimum FPS. The Athlon 64 system, on the other hand, spent only 14% of its time there. This is a difference of a whopping 121%! " So I am wanting to get a new system later this fall. I have read other reviews saying Intel is the way to go for gaming. I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3. I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?

[Tony Hill]

On 4 Sep 2005 08:15:25 -0700, Conservative.Nate@gmail.com wrote:
I read the following articlehttp://tinyurl.com/8s2aaon amdzone.com.

Hehe, www.amdzone.com is, not surprisingly, a VERY pro-AMD/anti-Intel
site, so don't expect to see anything except "AMD is the greatest"
from them! That being said, the article they are quoting is from a
much less biased source.
So I am wanting to get a new system later this fall. I have read otherreviews saying Intel is the way to go for gaming.

??? Really? When it comes to gaming Intel has been beaten pretty
soundly in virtually all tests I've seen since the Athlon64 was
released two years ago. Gaming is one area where AMD has the most
definite and obvious performance lead.
I am looking for the best performance in games and for burning dvds/cdsand web browsing. But the high intensity graphics will be from gameslike Doom 3.

AMD's Athlon64 chips are unquestionably the way to go for gaming
performance IMO. Their performance/dollar is a fair bit higher than
Intel's pretty much across the board, from their low-end (Socket 754)
Sempron models right up to their top-end Athlon64 FX chips. Dollar
for dollar the AMD chips are usually ~15-20% faster.
I don't want a system that will choke on the graphics. I was thikingabout the nvidia latest pci-e card.

If you can afford it, the nVidia GeForce 7800 GTX is the best out
there. Alternatively there is the 7800GT which offers close to the
same performance with a price tag that's about $100 less.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[bunboy]

I agree that a label is not what makes gaming interesting. I too have used
them all. Although I must admit this is the first time I broke my AMD
cherry a few weeks ago and so far am very satisfied/ FX 57. I also just
got two 7800 SLI and that's great too. Before that though it was a coup of
years or so of ATI which before that was an even longer period of Nvdia in
the ATI maybe bad driver support days.
The one thing you never hear about is a Creative fan boy because the
have been the masters of the monopoly game. They just quietly go about
doing nothing all that radical as far as I am concerned. There is not a
doubt in my mind that if creative had it's equivalent competitor like in the
graphics and cpu arena sound would be better also. Not that there is
anything greatly wrong with creative sound ,particularly when most people
play their games through low end speakers nowhere comparable to our high end
or even middle end home or these days even car speakers.
I play my games through my reasonably high end home stereo 5.1
surround system. The sub woofer is 800 watts and it actually hurts to get
hit by artillery in Battlefront 2 as I sit right next to it. Never the less
to say I can really tell the difference between my various creative live and
audigy cards is not really being too forward. they all sound fine to me but
not like my DVDs and music disks. I have been gaming since pong in the
seventies. I don't ever remember once pc gaming took effect a time when
anybody but Creative had any kind of a foot hold. I do remember cursing
them in the old DOS days when like 80% of computer problems were sound card
related.

"Tony Hill" <hilla_nospam_20@yahoo.ca> wrote in message
news:92jnh1ho20erfg6jp0935ae3cctc4sv2e2@4ax.com... On 4 Sep 2005 08:15:25 -0700, Conservative.Nate@gmail.com wrote:I read the following articlehttp://tinyurl.com/8s2aaon amdzone.com. Hehe, www.amdzone.com is, not surprisingly, a VERY pro-AMD/anti-Intel site, so don't expect to see anything except "AMD is the greatest" from them! That being said, the article they are quoting is from a much less biased source.So I am wanting to get a new system later this fall. I have read otherreviews saying Intel is the way to go for gaming. ??? Really? When it comes to gaming Intel has been beaten pretty soundly in virtually all tests I've seen since the Athlon64 was released two years ago. Gaming is one area where AMD has the most definite and obvious performance lead.I am looking for the best performance in games and for burning dvds/cdsand web browsing. But the high intensity graphics will be from gameslike Doom 3. AMD's Athlon64 chips are unquestionably the way to go for gaming performance IMO. Their performance/dollar is a fair bit higher than Intel's pretty much across the board, from their low-end (Socket 754) Sempron models right up to their top-end Athlon64 FX chips. Dollar for dollar the AMD chips are usually ~15-20% faster.I don't want a system that will choke on the graphics. I was thikingabout the nvidia latest pci-e card. If you can afford it, the nVidia GeForce 7800 GTX is the best out there. Alternatively there is the 7800GT which offers close to the same performance with a price tag that's about $100 less. ------------- Tony Hill hilla <underscore> 20 <at> yahoo <dot> ca

[YKhan]

Conservative.Nate@gmail.com wrote: So I am wanting to get a new system later this fall. I have read other reviews saying Intel is the way to go for gaming.

Those reviews must be several years old now. AMD has been tightening
its hold on the gaming market steady for the past 2-3 years now,
basically since the Athlon 64 first came out. Prior to that there was a
period of time (about 6 years ago to 4 years ago) when Intel and AMD
were trading top spot almost on a weekly basis. Then for a period of
one year, from about 4 years ago to about 3 years ago, Intel had the
crown for itself for about a year, as AMD dropped out to concentrate on
getting the Athlon 64 out.

Now, it's possible that AMD and Intel will switch positions once again
in this field, like they have in the past. But there's some evidence
that AMD will have this crown for several more years still. In the
transition from the Athlon XP to the Athlon 64, AMD took the time to
not only improve the design of chips, but it actually redesign some
very basic concepts of its chips. One example is that the ubiquitous
front-side bus (FSB), namely AMD got rid of it! The FSB was the method
by which PC chips had connected to their peripheral devices and its
memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
replaced it with two seperate connections, one for the memory and one
for the peripherals. Intel isn't expected to have a similar system till
at least 2007; and it's not likely that AMD will remain stagnant
waiting for Intel to catch up during that time.
I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3.

None of those tasks are all that demanding for today's generation of
processors.
I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?

Well, you touched on one thing that is very important these days: the
graphics card. The performance war at the CPU level has sort of taken a
backseat to the war of the video cards for gaming. It's not so much
Intel vs. AMD as it is Nvidia vs. ATI.

That being said, AMD does offer some interesting advantages to aid your
choice of video cards. These days video cards have gotten into a
dual-core battle of their own, ATI offers its Crossfire technology,
while Nvidia offers its SLI technology. Due to the seperated memory and
peripheral connection paths that AMD offers in Athlon 64 these days,
both Crossfire and SLI work much better under an AMD processor than in
an Intel processor. I think the numbers they have come up with
generally show that a Crossfire or SLI system will show a 40%
improvement under Intel, but an 80% improvement under AMD.

And that's not all, although this is something that's for the future,
and won't affect any processor purchase that you make today, there was
a rumour that AMD has decided to integrate a PCI-e interface directly
into the processor, which would offer even higher performance for SLI
or Crossfire. But that's something probably two years out too.

Yousuf Khan

[Guest]

On 5 Sep 2005 16:22:51 -0700, "YKhan" <yjkhan@gmail.com> wrote:
Conservative.Nate@gmail.com wrote:
....snip... I am looking for the best performance in games and for burning dvds/cds and web browsing. But the high intensity graphics will be from games like Doom 3.None of those tasks are all that demanding for today's generation ofprocessors.
Maybe straight copying is not demanding. Bur burning DVDs from .avi
files is (unless NeroVision Express 3 is a piece of crap, which IMO
it's not). When it does encoding, both of my (admittedly not-so-new)
Opterons 242 are loaded above 90%, and graphics card takes no part of
the job.
I don't want a system that will choke on the graphics. I was thiking about the nvidia latest pci-e card. Any thoughts on intel vs AMD?Well, you touched on one thing that is very important these days: thegraphics card. The performance war at the CPU level has sort of taken abackseat to the war of the video cards for gaming. It's not so muchIntel vs. AMD as it is Nvidia vs. ATI.That being said, AMD does offer some interesting advantages to aid yourchoice of video cards. These days video cards have gotten into adual-core battle of their own, ATI offers its Crossfire technology,while Nvidia offers its SLI technology. Due to the seperated memory andperipheral connection paths that AMD offers in Athlon 64 these days,both Crossfire and SLI work much better under an AMD processor than inan Intel processor. I think the numbers they have come up withgenerally show that a Crossfire or SLI system will show a 40%improvement under Intel, but an 80% improvement under AMD.And that's not all, although this is something that's for the future,and won't affect any processor purchase that you make today, there wasa rumour that AMD has decided to integrate a PCI-e interface directlyinto the processor, which would offer even higher performance for SLIor Crossfire. But that's something probably two years out too. Yousuf Khan

Agree with all said here about the advantages of A64. So much so that
I'd advice to multiply it by 2. Even though the fastest A64 X2 has a
notch slower clock than the fastest single core, it gets ahead if you
are multitasking. Or, if your pockets allow for it, go for dual
dual-core Opteron, making it a quad. Maybe today's games can't take
real advantage of multithreading, but I bet the games of tomorrow (and
not only games) are already being coded to use multiple cores to their
advantage.

NNN

[Wes Newell]

On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:
not only improve the design of chips, but it actually redesign some very basic concepts of its chips. One example is that the ubiquitous front-side bus (FSB), namely AMD got rid of it! The FSB was the method by which PC chips had connected to their peripheral devices and its memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and replaced it with two seperate connections, one for the memory and one for the peripherals.

For clearity, AMD didn't get rid of the FSB, they just stopped calling it
a FSB, even though that's what it still is, by definition. They did
however move the memory controller onto the cpu, so that ram data now has
it's own data path to the CPU. This move, and not the move to an HT link
for the FSB is where the major performance gain was made. With the move to
the seperate memory bus, the FSB (now a serial HT link, instead of a
paralell bus) speed is of little importance.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
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[George Macdonald]

On Tue, 06 Sep 2005 06:14:02 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:
On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote: not only improve the design of chips, but it actually redesign some very basic concepts of its chips. One example is that the ubiquitous front-side bus (FSB), namely AMD got rid of it! The FSB was the method by which PC chips had connected to their peripheral devices and its memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and replaced it with two seperate connections, one for the memory and one for the peripherals.For clearity, AMD didn't get rid of the FSB, they just stopped calling ita FSB, even though that's what it still is, by definition.

The term FSB came about with Intel's Pentium Pro, where the dual chip
CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
<-> L2 cache data as well as I/O and memory transfers. By definition, a
FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
cache transfers. To me calling AMD's HT a FSB is about as valid as
continuing to use North Bridge & South Bridge for the two chips normally
used in a chipset - it's not really applicable any more but people will say
it as a convenience term
They didhowever move the memory controller onto the cpu, so that ram data now hasit's own data path to the CPU. This move, and not the move to an HT linkfor the FSB is where the major performance gain was made. With the move tothe seperate memory bus, the FSB (now a serial HT link, instead of aparalell bus) speed is of little importance.

As recently discussed here, HyperTransport is not a serial bus - it *is*
packetized and it is point-to-point/uni-directional but each byte-width
path has a separate clock signal and the chip/system designers have to pay
close attention to clock skew.

As far as speed, with current Athlon64 systems, the 2-byte-wide down-link
from CPU->chipset->PCI-e(x16) is, in theory, maxed out at the 1GHz clock
rate. Put another way, the current PCI-e x16 graphics path has a max
bandwidth of 4.1GB/s; the HT down-link has a max bandwidth of 4GB/s so in
theory, at least, it would be possible for memory->graphics transfers to
saturate the HT down-link.

I don't think this is a problem for the moment but add in that the 4GB/s HT
up-link for an integrated graphics chipset could be seriously stressed and
cause HT traffic contention, it could lead to problems down the road... as
well as supply ammo to anti-AMD marketing efforts. So yes, speed of HT is
an issue and the integrated PCI-e that AMD is adding will help mitigate
those err, concerns.

--
Rgds, George Macdonald

[Guest]

>Or, if your pockets allow for it, go for dualdual-core Opteron, making it a quad. Maybe today's games can't takereal advantage of multithreading, but I bet the games of tomorrow (andnot only games) are already being coded to use multiple cores to theiradvantage.

Forgive me, I have not read much about Opteron chips. Are you saying
a system with dual 64 bit Opteron chips is about the same as what a
QUAD A64 X2 would be ?

[YKhan]

Conservative.N...@gmail.com wrote:Or, if your pockets allow for it, go for dualdual-core Opteron, making it a quad. Maybe today's games can't takereal advantage of multithreading, but I bet the games of tomorrow (andnot only games) are already being coded to use multiple cores to theiradvantage. Forgive me, I have not read much about Opteron chips. Are you saying a system with dual 64 bit Opteron chips is about the same as what a QUAD A64 X2 would be ?

No, A64 systems are limited to one and only one CPU socket. So if you
have a dual-core A64, then that's all you're ever going to get: two
cores. However, Opteron workstations often have dual sockets, and
dual-core Opterons in each socket will mean that you have upto four
cores.

Yousuf Khan

[YKhan]

To me, a bus would be a multi-drop access medium, with multiple devices
(including CPUs) all sharing a single data path between each other.
Hypertransport is a point-to-point interface, you can only connect to
one other device with each HT link. This would be much the same as old
collision-based Ethernet vs. switched Ethernet.

Yousuf Khan

[Wes Newell]

On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:
For clearity, AMD didn't get rid of the FSB, they just stopped calling ita FSB, even though that's what it still is, by definition. The term FSB came about with Intel's Pentium Pro, where the dual chip CPU/L2 cache package contained a BSB (Back Side Bus) connection between the CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU <-> L2 cache data as well as I/O and memory transfers. By definition, a FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2 cache transfers. To me calling AMD's HT a FSB is about as valid as continuing to use North Bridge & South Bridge for the two chips normally used in a chipset - it's not really applicable any more but people will say it as a convenience term
FSB by definition connects the CPU to the chipset. HT link by definition
is just that, any bus using HT technolog and is not limited to
connections between a cpu and a chipset. So given the choice of
calling the bus a FSB, or the HT link, FSB fits the bill while HT link
only describes the type of bus, not the bus itself. IOW's using the term
FSB specifically refers to the connection between the CPU and chipset,
while using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus, but
that's generic in nature and could even refer to the memory bus since it's
a part of the system. So, imo, the bus conncetion between the cpu and
chipset is still a FSB, thus specifically stating what the two ends
actually connect to. Simply calling it an HT link doesn't descibe any
particular bus, and shouldn't be assumed that it means a conncetion
between a xpu and its chipset, as HT links are currently being used for
other purposes. Be it convenient or not, it's still there.
They didhowever move the memory controller onto the cpu, so that ram data now hasit's own data path to the CPU. This move, and not the move to an HT linkfor the FSB is where the major performance gain was made. With the move tothe seperate memory bus, the FSB (now a serial HT link, instead of aparalell bus) speed is of little importance. As recently discussed here, HyperTransport is not a serial bus - it *is* packetized and it is point-to-point/uni-directional but each byte-width path has a separate clock signal and the chip/system designers have to pay close attention to clock skew.
I'll go with you on this. Probably a paralell packet network would
describe it better.

--
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Need good help? Provide all system info with question.
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[keith]

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:For clearity, AMD didn't get rid of the FSB, they just stopped calling ita FSB, even though that's what it still is, by definition. The term FSB came about with Intel's Pentium Pro, where the dual chip CPU/L2 cache package contained a BSB (Back Side Bus) connection between the CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU <-> L2 cache data as well as I/O and memory transfers. By definition, a FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2 cache transfers. To me calling AMD's HT a FSB is about as valid as continuing to use North Bridge & South Bridge for the two chips normally used in a chipset - it's not really applicable any more but people will say it as a convenience term FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side <cache> bus"
of the P6. The P5 had no "FSB".
HT link by definition is just that, any bus using HT technolog and is not limited to connections between a cpu and a chipset.

Only in your mind. It is in no way an "FSB", since the term is now
meaningless. The memory bus is elsewhere, so if there *IS* an "FSB" it's
the memory bus(ses), not the HT channel. The caches are on the
"back-side" of the memory interface, not other procesors or I/O.
So given the choice of calling the bus a FSB, or the HT link, FSB fits the bill while HT link only describes the type of bus, not the bus itself.

FSB doesn't describe it's function at all. What's the "back side" of the
HT link?
IOW's using the term FSB specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are on
the other side (back side) of the P6 memory bus. That architecture was
around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there, since it
no longer describes any function.

while using the term HT link could be any of many different type of connections an HT link is used for since it's used in many more applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.
but that's generic in nature and could even refer to the memory bus since it's a part of the system.

Since it is the intervace from the processor to the "system", it still
makes sense. "FSB" makes *no* sense, since it's not on the "front" side
of anything.
So, imo, the bus conncetion between the cpu and chipset is still a FSB, thus specifically stating what the two ends actually connect to. Simply calling it an HT link doesn't descibe any particular bus, and shouldn't be assumed that it means a conncetion between a xpu and its chipset, as HT links are currently being used for other purposes. Be it convenient or not, it's still there.

Your opinion and $2 may be useful in a Starbuck's. They don't much care
if you're wrong, as long as you have $2.
They didhowever move the memory controller onto the cpu, so that ram data nowhas it's own data path to the CPU. This move, and not the move to an HTlink for the FSB is where the major performance gain was made. With themove to the seperate memory bus, the FSB (now a serial HT link, insteadof a paralell bus) speed is of little importance. As recently discussed here, HyperTransport is not a serial bus - it *is* packetized and it is point-to-point/uni-directional but each byte-width path has a separate clock signal and the chip/system designers have to pay close attention to clock skew. I'll go with you on this. Probably a paralell packet network would describe it better.

Whatever, but it is *NOT* an "FSB". AMD has broken out of that system
architecture. ...much like Intel broke into it by moving the L2 traffic
to the *BACK-SIDE* bus.

--
Keith

[Yousuf Khan]

keith wrote: Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".

Maybe in those days it was better known as the "local bus".

Yousuf Khan

[Wes Newell]

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote: FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".
Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

While the term may have originated the way you say, it was then later used
to indicate the connection between the CPU and the chipset. Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory data
now has own single use bus for the memory. The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.
HT link by definition is just that, any bus using HT technolog and is not limited to connections between a cpu and a chipset. Only in your mind. It is in no way an "FSB", since the term is now meaningless. The memory bus is elsewhere, so if there *IS* an "FSB" it's the memory bus(ses), not the HT channel. The caches are on the "back-side" of the memory interface, not other procesors or I/O.
And I thought only the government could take something so simple and
fiubar.
So given the choice of calling the bus a FSB, or the HT link, FSB fits the bill while HT link only describes the type of bus, not the bus itself. FSB doesn't describe it's function at all. What's the "back side" of the HT link?
What HT link? Ht links are used everywhere. AFAIK, they don't need a
backside. They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the chipset,
I'd just answer that it's in the same place as back side of the K7 CPU's
FSB. You're really digging a hole for yourself here.
IOW's using the term FSB specifically refers to the connection between the CPU and chipset, No, it doesn't. I specifically refers to the fact that the caches are on the other side (back side) of the P6 memory bus. That architecture was around for a while, so it stuck. There was no "FSB" in the P5 architecture. It's an invention of the P6 and should stay there, since it no longer describes any function.
Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset. while using the term HT link could be any of many different type of connections an HT link is used for since it's used in many more applications than just a FSB. Some refer to the bus as a system bus, "System bus" works for me. I/O bus makes more sense.
Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
buses. So how are you going to distinquish which one you are talking about
if you just use system bus? Damn, I wonder if FSB would do that?:-)
I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
an I/O bus.

--
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Need good help? Provide all system info with question.
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[George Macdonald]

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:
On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote: FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let'ssee just how many people you can convince of that.:-)

No, the K7s had (the equivalent of) a FSB though I'm not sure AMD ever
called it that IIRC.
While the term may have originated the way you say, it was then later usedto indicate the connection between the CPU and the chipset. Now, that sameconnection is the HT link of the K8. So it only makes sense to use thesame terminology for the very specific connection even though memory datanow has own single use bus for the memory. The FSB still carries all otherIO operations to/from the system. Once they move all this into the CPU,there will no longer be a FSB. Until then, a duck by any other name isstill a duck.

NO - the HT is more akin to the Intel Hub interface or the VIA-Link
interconnect between memory controller/AGP chip and the I/O chip; it was
AMD's attempt to establish a standard for that type of traffic... since
Intel had locked theirs up with licensing fees. Much of the old PC North
Bridge arbitration logic is now in the K8 CPU - it has to be to route to
the various memory address spaces and for DMA transfers.
So given the choice of calling the bus a FSB, or the HT link, FSB fits the bill while HT link only describes the type of bus, not the bus itself. FSB doesn't describe it's function at all. What's the "back side" of the HT link?What HT link? Ht links are used everywhere. AFAIK, they don't need abackside. They function fully indepentant of other buses. If I assume youare talking about the HT link used to connect the K8 cpu's to the chipset,I'd just answer that it's in the same place as back side of the K7 CPU'sFSB. You're really digging a hole for yourself here.

The equivalent of FSB on a K8 CPU is inside the CPU die - anything that
gets out to HT is already defined as I/O traffic. In no way is it a FSB.

--
Rgds, George Macdonald

[Felger Carbon]

"Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
news:pan.2005.09.07.06.03.43.197405@TAKEOUTverizon.net... On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote: FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side
<cache> bus" of the P6. The P5 had no "FSB". Under your definition of FSB, then no AMD CPU's have ever had a FSB.
Let's see just how many people you can convince of that.:-)

Wes, are you saying no AMD chip ever had an L2 cache hung off the back
of the CPU? Wow, is _my_ memory ever going south! ;-)

[Wes Newell]

On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:
"Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message news:pan.2005.09.07.06.03.43.197405@TAKEOUTverizon.net... On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:> FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB". Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's see just how many people you can convince of that.:-) Wes, are you saying no AMD chip ever had an L2 cache hung off the back of the CPU? Wow, is _my_ memory ever going south! ;-)

Well, that's was what I said, but I wasn't thinking back past the K7 and
K8's, and I actually never paid much attention to what they called the
bus to the earlier cpu's that had cache on the MB. Was that an L2 cache? I
thought it was L1. Too long ago to remember and I'm too lazy to look it up.:-)
And I just remembered that the Slot A k7's had it's L2 cache on the cpu
board too, and not in the cpu die, but I don't recall AMD or anyone else
using back side bus for it.

--
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Need good help? Provide all system info with question.
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[keith]

On Wed, 07 Sep 2005 18:57:23 +0000, Wes Newell wrote:
On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote: "Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message news:pan.2005.09.07.06.03.43.197405@TAKEOUTverizon.net... On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote: > >> FSB by definition connects the CPU to the chipset. > > Nope. As George stated, it was in opposition the "back-side <cache> bus" > of the P6. The P5 had no "FSB". > Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's see just how many people you can convince of that.:-) Wes, are you saying no AMD chip ever had an L2 cache hung off the back of the CPU? Wow, is _my_ memory ever going south! ;-) Well, that's was what I said, but I wasn't thinking back past the K7 and K8's, and I actually never paid much attention to what they called the bus to the earlier cpu's that had cache on the MB.

K7s had the L2 on the "back side". It wasn't hooked into the external
bus, as was socket-7 (and before).
Was that an L2 cache? I thought it was L1.

Modern processors have *long* had seperate I and D L1s, burried in the
instruction-fetch and load-store elements. The K7s L2 is certainly hung
off the "back-side", meaning not connected to the system bus. The K8
further seperates the I/O and memory busses, so there is no longer
soethign even resembling a "front-side bus". There is (are) memory
bus(ses) and HT link(s). Alghough, the HT link isn't just an I/O bus. It
also crries coherency information (but I/O must be cache coherent too).
Too long ago to remember and I'm too lazy to look it up.:-) And I just remembered that the Slot A k7's had it's L2 cache on the cpu board too, and not in the cpu die, but I don't recall AMD or anyone else using back side bus for it.

I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2. Even the K6-III has an on-chip L2, but allows an
on-board L3 (mine has a 2MB L3).

--
Keith

[Take a Walk]

On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:

I'm from Missouri (close, but not really). I never remember a slot-A K7with on-board L2. Even the K6-III has an on-chip L2, but allows anon-board L3 (mine has a 2MB L3).

Slot-A didn't have on-die L2 cache.
K7-500 512K L2 (has a 650Mhz core)
http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg

[keith]

On Wed, 07 Sep 2005 16:53:57 -0500, Ed wrote:
On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:I'm from Missouri (close, but not really). I never remember a slot-A K7with on-board L2. Even the K6-III has an on-chip L2, but allows anon-board L3 (mine has a 2MB L3). Slot-A didn't have on-die L2 cache.

I didn't say it did. Note that the Slot-1 PII didn't have an integrated
cache either, but the cache was still on the "back side" of the chip. The
Slot-A K7 was no different.
K7-500 512K L2 (has a 650Mhz core) http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg

Sheesh, learn *SOMETHING*! Do start with reading comprehension.

--
Keith

[Tony Hill]

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote:
On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote: FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let'ssee just how many people you can convince of that.:-)

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have a
frontside bus (Intel had already gone to integrated cache by this
time).

Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
is only kinda-sorta a bus in itself. Really it's more of a
point-to-point link, though it's in that fuzzy area that blurs the
lines between the two a bit (where the GTL+ bus used in the P6 is
definitely a bus and Hypertransport is definitely not a bus, EV6 falls
somewhere in between).
While the term may have originated the way you say, it was then later usedto indicate the connection between the CPU and the chipset.

Yes, a lot of people incorrectly refer to the a connection between the
CPU and the chipset as a "Front Side Bus". Just because lots of
people make a mistake that doesn't mean that they are right.

People also still call the memory controller the "northbridge" and the
I/O chip a "southbridge", which also makes no sense given that they
are no longer being connected via PCI and they usually aren't bridges
at all. Again, just because people incorrectly use a term doesn't
make it correct.
Now, that sameconnection is the HT link of the K8. So it only makes sense to use thesame terminology for the very specific connection even though memory datanow has own single use bus for the memory.

It doesn't make any sense with the AthlonXP or the P4 and it makes
MUCH less sense with the Athlon64/Opteron. Just because it's a common
mistake doesn't make it any less of a mistake.
The FSB still carries all otherIO operations to/from the system. Once they move all this into the CPU,there will no longer be a FSB. Until then, a duck by any other name isstill a duck.

Yes, but that still doesn't make a goose a duck, even if lots of
people mix the two of them up.
FSB doesn't describe it's function at all. What's the "back side" of the HT link?What HT link? Ht links are used everywhere. AFAIK, they don't need abackside.

The point is that you can't have a "front side bus" unless you have a
corresponding "back side bus". Hypertransport does not have such a
corresponding back side so therefore it's not the "front side" of
anything.

Given that it's not the 'front side' of anything and, as others have
mentioned, it's not a 'bus' at all then it DEFINITELY is not a "Front
Side Bus".
They function fully indepentant of other buses. If I assume youare talking about the HT link used to connect the K8 cpu's to the chipset,I'd just answer that it's in the same place as back side of the K7 CPU'sFSB. You're really digging a hole for yourself here.

The original Athlon had a backside bus with to the cache chips on the
cartridge. This was later removed with the "Thunderbird" chips with
integrated cache. As such, from the "Thunderbird" on forward
(including all AthlonXP chips) there was no FSB on the AthlonXP. Same
goes for the PIII from the "Coppermine" onwards as well as ALL P4
chips. None of those have FSBs, despite the fact that many people
incorrectly use the term to describe the system bus of said chips.
IOW's using the term FSB specifically refers to the connection between the CPU and chipset, No, it doesn't. I specifically refers to the fact that the caches are on the other side (back side) of the P6 memory bus. That architecture was around for a while, so it stuck. There was no "FSB" in the P5 architecture. It's an invention of the P6 and should stay there, since it no longer describes any function.Why are you stuck on the Pentium Pro. FSB has been used for years toindicate the connection between the CPU and the chipset.

The term "Front Side Bus" was never used with the Pentium chips
because there was only one bus. FSB came into computer use with the
PentiumPro where Intel introduced a chip with a Frontside Bus
(connecting to main memory and I/O) and a Backside bus (connecting to
cache). The terminology continued through the PII and early PIII
chips, as well as early Athlon chips, as they had two buses, one for
memory and I/O and the other for cache. For chips with only a single
bus the term "FSB" makes no sense. Never has and never will, no
matter how many people make such a mistake.

With the Athlon64 and Opteron it's just more obviously incorrect than
it is with the AthlonXP and P4 chips.
while using the term HT link could be any of many different type of connections an HT link is used for since it's used in many more applications than just a FSB. Some refer to the bus as a system bus, "System bus" works for me. I/O bus makes more sense.Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all systembuses. So how are you going to distinquish which one you are talking aboutif you just use system bus? Damn, I wonder if FSB would do that?:-)I/O bus. Ditto, and you can throw HTlink into the mix too since it is alsoan I/O bus.

Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
point-to-point link. PCI-E and AGP are also definitely not buses,
though I expect many people to incorrectly call them such. PCI and
ISA are buses

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[Tony Hill]

On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote: Too long ago to remember and I'm too lazy to look it up.:-) And I just remembered that the Slot A k7's had it's L2 cache on the cpu board too, and not in the cpu die, but I don't recall AMD or anyone else using back side bus for it.I'm from Missouri (close, but not really). I never remember a slot-A K7with on-board L2.

There were a *few* Slot-A K7 chips that had integrated L2, but they
were only released for compatibility purposes (much like what Intel
did with some of their later Slot-1 PIII chips, though AMD released
far fewer of such chips). You might even be able to find someone
still selling such a beast if you look hard enough, just do a search
for "Thunderbird Slot-A".

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[Wes Newell]

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote:On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:> FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let'ssee just how many people you can convince of that.:-) Not true at all. The original AMD Athlon had both a front-side bus, connecting the CPU to the chipset, I/O and memory, and a backside bus that connected the CPU to the cache chips on the Slot-A cartridge. This was actually the last x86 CPU that I'm aware of which did have a frontside bus (Intel had already gone to integrated cache by this time).

You're partially right anyway.:-) Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is only kinda-sorta a bus in itself. Really it's more of a point-to-point link, though it's in that fuzzy area that blurs the lines between the two a bit (where the GTL+ bus used in the P6 is definitely a bus and Hypertransport is definitely not a bus, EV6 falls somewhere in between).
You're out to lunch here for the most part.
While the term may have originated the way you say, it was then laterused to indicate the connection between the CPU and the chipset. Yes, a lot of people incorrectly refer to the a connection between the CPU and the chipset as a "Front Side Bus". Just because lots of people make a mistake that doesn't mean that they are right.
Wrong. FSB is defined as the bus connection between the CPU and chipset.
AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4. If
you break down the term, it's pretty simple. Front side, meaning not the
back side, and bus. A bus is a collection of 1 or more electrical
connections between 2 or more points. The type of bus (standard, EV6, HT
link, or any other type) is of no concern.
People also still call the memory controller the "northbridge" and the I/O chip a "southbridge", which also makes no sense given that they are no longer being connected via PCI and they usually aren't bridges at all. Again, just because people incorrectly use a term doesn't make it correct.
What? The northbridge has much more in it than just a memory controller.
And the K8 northbridge doesn't even have a memory controller in it.
Now, that sameconnection is the HT link of the K8. So it only makes sense to use thesame terminology for the very specific connection even though memorydata now has own single use bus for the memory. It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH less sense with the Athlon64/Opteron. Just because it's a common mistake doesn't make it any less of a mistake.
Well, AMD and Intel disagree, as do I. ANd it's used for one purpose IMO,
to distinquish which fricking bus you are talking about.
The FSB still carries all otherIO operations to/from the system. Once they move all this into the CPU,there will no longer be a FSB. Until then, a duck by any other name isstill a duck. Yes, but that still doesn't make a goose a duck, even if lots of people mix the two of them up.
Just out of curiosty, I'd like you to tell me what the name of the bus
is between the CPU and the chipset. And I don't mean what type of bus.
It's already known to be an HT link. So what's the name you want to give
it so that when someone refers to it by that name they will know exactly
which bus you are talking about and where it connects. And it has to be
specific. Sytem bus doesn't cut, there's many system buses. CPU bus
doesn't cut it as there are many cpu busses if you count the internal
busses. I say FSB. I'm waiting for a better one from you.
The point is that you can't have a "front side bus" unless you have a corresponding "back side bus". Hypertransport does not have such a corresponding back side so therefore it's not the "front side" of anything.
I'll give you two options. Take your pick. (1) The internal bus to the L2
cache is the back side bus. It just internal now. (2) Why must there be a
BSB at all? FSB is more of a designation for a certain bus rather than
actually describing it's location. It connects between the CPU and
chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
complaints of calling it a FSB then. That's what AMD called it.
They function fully indepentant of other buses. If I assume youare talking about the HT link used to connect the K8 cpu's to thechipset, I'd just answer that it's in the same place as back side of theK7 CPU's FSB. You're really digging a hole for yourself here. The original Athlon had a backside bus with to the cache chips on the cartridge. This was later removed with the "Thunderbird" chips with integrated cache. As such, from the "Thunderbird" on forward (including all AthlonXP chips) there was no FSB on the AthlonXP.

They didn't remove the L2 cache. It was just moved inside the die. You
think that memory just magically connects to the rest of the CPU without
a bus. I sure as hell wish I'd known I could do that when I was designing
memory controllers.:-)
Same goes for the PIII from the "Coppermine" onwards as well as ALL P4 chips. None of those have FSBs, despite the fact that many people incorrectly use the term to describe the system bus of said chips.
I'm not an Intel user, but I assume you are as wrong about this as you are
about the AMD's not having a FSB.
Why are you stuck on the Pentium Pro. FSB has been used for years toindicate the connection between the CPU and the chipset. The term "Front Side Bus" was never used with the Pentium chips because there was only one bus. FSB came into computer use with the PentiumPro where Intel introduced a chip with a Frontside Bus (connecting to main memory and I/O) and a Backside bus (connecting to cache).

How many times must you guys write this? No one argues that point.
The terminology continued through the PII and early PIII chips, as well as early Athlon chips, as they had two buses, one for memory and I/O and the other for cache. For chips with only a single bus the term "FSB" makes no sense. Never has and never will, no matter how many people make such a mistake.
It makes all the sense in the world defined as the connection between the
CPU and chipset. If not, tell me what does. All you people have said it's
not right, yet none of you have come up with a definitive name for the
bus. I wonder if that's why it's stuck around so long, since I've seen it
defined as just that, the bus between the CPU and chipset.
With the Athlon64 and Opteron it's just more obviously incorrect than it is with the AthlonXP and P4 chips.
Tell AMD and Intel, they need some humor too.
Hypertransport is NOT an 'bus' in any way, shape or form. HT is a point-to-point link. PCI-E and AGP are also definitely not buses, though I expect many people to incorrectly call them such. PCI and ISA are buses

I don't know what you think a bus is. perhaps you should give your
definition of a bus, and not a school bus. Every definition of bus I've
seen says it an electrical pathway. So unless the HT link works without
electricty, it's a bus. As are all the others you claim aren't.

And now the killer punch. From;

http://www.hypertransport.org/consortium/cons_faqs.cfm

9. How does HyperTransport technology compare to other bus technologies?

As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,
HyperTransport provides a far simplier electrical interface, but with much
greater bandwidth. Instead of a wide, address/data/control multidrop,
shared bus such as implemented by PCI, PCI-X or SysAD technologies,
HyperTransport deploys narrow, but very fast unidirectional links to carry
both data and command information encoded into packets. Unidirectional
links provide significantly better signal integrity at high speeds and
enable much faster data transfers with low-power 1.2V LVDS signals. In
addition, link widths can be asymmetrical, meaning that 2 bit wide links
can easily connect to 8 bit wide links and 8 bit wide links can connect to
16 or 32 bit wide links and so on. Thus, the HyperTransport Technology
eliminates the problems associated with high speed parallel buses with
their many noisy bus signals (multiplexed data/address, and clock and
control signals) while providing scalable bandwidth wherever it is needed
in the system. As compared to newer serial I/O technologies such as
RapidIO and PCI Express, HyperTransport shares some raw bandwidth
characteristics, but is significantly different in some key
characteristics.
*****Read this pargraph carefully********
HyperTransport was designed to support both CPU-to-CPU
communications as well as CPU-to-I/O transfers, thus, it features very low
latency. Consequently, it has been incorporated into multiple x86 and MIPS
architecture processors as an integrated front-side bus.
*And don't miss this................................. ^^^^^^^^^ *

Serial technologies such as PCI Express and RapidIO require
serial-deserializer interfaces and have the burden of extensive overhead
in encoding parallel data into serial data, embedding clock information,
re-acquiring and decoding the data stream. The parallel technology of
HyperTransport needs no serdes and clock encoding overhead making it far
more efficient in data transfers.

I rest my case.;-)

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

[dannysdailys]

I believe this is a "setup" question. AMD has had superior processors
for quite some time now. Where have you been? AMD's superiority
began with the first Athlon processors, they had the first 64bit and
the first dual comsumer processor. It's dual kicks Intels butt big
time. Almost makes Intel look like they're in the dark ages they
are.

Assuming you already know the answer; what you may not know that most
AMD processors are unlocked and are quite easily over clocked and
Intel's are not. There is a reason, if Intels run any hotter, you
could heat your house with them.

Cooling, while not a glamorious subject, is the only thing giving you
a serious edge. Edge? Yeah, edge for tweaking, and edge for
longevity.

Gaming is not the only thing that gets a processor hot. I encode DVDs
from my old VCR tapes and writing chapters, pegs my processor for up
to 1/2 hour. That is much more an indicator of a faster processor,
then gaming is. Gaming stresses more then just the processor.

Using a TT Silent Boost cooler, my processor only gains about 4
degrees f. That's amazing.

Also, don't forget the video is just as important. Without good
video, all the processor power in the world won't help you for
gaming.

[Del Cecchi]

Wes Newell wrote:
*
snip Serial technologies such as PCI Express and RapidIO require serial-deserializer interfaces and have the burden of extensive overhead in encoding parallel data into serial data, embedding clock information, re-acquiring and decoding the data stream. The parallel technology of HyperTransport needs no serdes and clock encoding overhead making it far more efficient in data transfers. I rest my case.;-)

The last paragraph you quote, shown above, is Clintonian at best, with
respect to comparing the physical aspects of HT and PCI-E.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

[keith]

On Thu, 08 Sep 2005 21:41:36 -0400, Tony Hill wrote:
On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote: Too long ago to remember and I'm too lazy to look it up.:-) And I just remembered that the Slot A k7's had it's L2 cache on the cpu board too, and not in the cpu die, but I don't recall AMD or anyone else using back side bus for it.I'm from Missouri (close, but not really). I never remember a slot-A K7with on-board L2. There were a *few* Slot-A K7 chips that had integrated L2, but they were only released for compatibility purposes (much like what Intel did with some of their later Slot-1 PIII chips, though AMD released far fewer of such chips). You might even be able to find someone still selling such a beast if you look hard enough, just do a search for "Thunderbird Slot-A".

I meant the cache on the board (system bus), as opposed to "integrated"
or on the cartridge (on the "back-side").

--
Keith

[keith]

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote:On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote: On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:> FSB by definition connects the CPU to the chipset. Nope. As George stated, it was in opposition the "back-side <cache> bus" of the P6. The P5 had no "FSB".Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let'ssee just how many people you can convince of that.:-) Not true at all. The original AMD Athlon had both a front-side bus, connecting the CPU to the chipset, I/O and memory, and a backside bus that connected the CPU to the cache chips on the Slot-A cartridge. This was actually the last x86 CPU that I'm aware of which did have a frontside bus (Intel had already gone to integrated cache by this time).

Just because the cache is integrated doesn't mean the cache isn't on the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.
Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is only kinda-sorta a bus in itself. Really it's more of a point-to-point link, though it's in that fuzzy area that blurs the lines between the two a bit (where the GTL+ bus used in the P6 is definitely a bus and Hypertransport is definitely not a bus, EV6 falls somewhere in between).

Works for me.
While the term may have originated the way you say, it was then laterused to indicate the connection between the CPU and the chipset. Yes, a lot of people incorrectly refer to the a connection between the CPU and the chipset as a "Front Side Bus". Just because lots of people make a mistake that doesn't mean that they are right.

Yep! It ignores the reason it was called the "front-side bus" to begin
with.
People also still call the memory controller the "northbridge" and the I/O chip a "southbridge", which also makes no sense given that they are no longer being connected via PCI and they usually aren't bridges at all. Again, just because people incorrectly use a term doesn't make it correct.

As long as there is an off-chip memory controller and high-speed
peripherals on the "bridge", it's proper to call it a "north-bridge". If
there is a low-spped bridge hanging off that, "south-bridge" is a useful
concept.
Now, that sameconnection is the HT link of the K8. So it only makes sense to use thesame terminology for the very specific connection even though memorydata now has own single use bus for the memory. It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH less sense with the Athlon64/Opteron. Just because it's a common mistake doesn't make it any less of a mistake.

Why doesn't "front-side bus" work with the P4 or K7? The cache is still
on the "back side" of the processor, even though it's on the chip.

<snip>
They function fully indepentant of other buses. If I assume youare talking about the HT link used to connect the K8 cpu's to thechipset, I'd just answer that it's in the same place as back side of theK7 CPU's FSB. You're really digging a hole for yourself here. The original Athlon had a backside bus with to the cache chips on the cartridge. This was later removed with the "Thunderbird" chips with integrated cache. As such, from the "Thunderbird" on forward (including all AthlonXP chips) there was no FSB on the AthlonXP. Same goes for the PIII from the "Coppermine" onwards as well as ALL P4 chips. None of those have FSBs, despite the fact that many people incorrectly use the term to describe the system bus of said chips.

No, the back side bus wasn't removed. It was integrated onto the chip.
The architecture is the same, if the parts moved around.
> IOW's using the term FSB> specifically refers to the connection between the CPU and chipset, No, it doesn't. I specifically refers to the fact that the caches are on the other side (back side) of the P6 memory bus. That architecture was around for a while, so it stuck. There was no "FSB" in the P5 architecture. It's an invention of the P6 and should stay there, since it no longer describes any function.Why are you stuck on the Pentium Pro. FSB has been used for years toindicate the connection between the CPU and the chipset. The term "Front Side Bus" was never used with the Pentium chips because there was only one bus. FSB came into computer use with the PentiumPro where Intel introduced a chip with a Frontside Bus (connecting to main memory and I/O) and a Backside bus (connecting to cache). The terminology continued through the PII and early PIII chips, as well as early Athlon chips, as they had two buses, one for memory and I/O and the other for cache. For chips with only a single bus the term "FSB" makes no sense. Never has and never will, no matter how many people make such a mistake.

I dissagree. The back-side bus was integrated onto the chip. Again, the
memory architecture was the same.
With the Athlon64 and Opteron it's just more obviously incorrect than it is with the AthlonXP and P4 chips.

It *is* incorrect, not so with the P4 or K7.
> while> using the term HT link could be any of many different type of> connections an HT link is used for since it's used in many more> applications than just a FSB. Some refer to the bus as a system bus, "System bus" works for me. I/O bus makes more sense.Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all systembuses. So how are you going to distinquish which one you are talkingabout if you just use system bus? Damn, I wonder if FSB would dothat?:-) I/O bus. Ditto, and you can throw HTlink into the mix too sinceit is also an I/O bus.
Hypertransport is NOT an 'bus' in any way, shape or form. HT is a point-to-point link. PCI-E and AGP are also definitely not buses, though I expect many people to incorrectly call them such. PCI and ISA are buses

True enough. Apparently some people call ducks geese too. ;-)

--
Keith

[Wes Newell]

On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
Wes Newell wrote: * snip Serial technologies such as PCI Express and RapidIO require serial-deserializer interfaces and have the burden of extensive overhead in encoding parallel data into serial data, embedding clock information, re-acquiring and decoding the data stream. The parallel technology of HyperTransport needs no serdes and clock encoding overhead making it far more efficient in data transfers. I rest my case.;-) The last paragraph you quote, shown above, is Clintonian at best, with respect to comparing the physical aspects of HT and PCI-E.

You snipped the portion I had highlighted. I didn't even read this part.
Nor do I have any comments on it. If you have a problem with it. i suggest
you contact the people that wrote it. If Clintonian refers to refers to
our lying crooked x pres, those are are fighting words. I never voted for
the lowlife.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

[Del Cecchi]

Wes Newell wrote: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:Wes Newell wrote:*snipSerial technologies such as PCI Express and RapidIO requireserial-deserializer interfaces and have the burden of extensive overheadin encoding parallel data into serial data, embedding clock information,re-acquiring and decoding the data stream. The parallel technology ofHyperTransport needs no serdes and clock encoding overhead making it farmore efficient in data transfers.I rest my case.;-)The last paragraph you quote, shown above, is Clintonian at best, withrespect to comparing the physical aspects of HT and PCI-E. You snipped the portion I had highlighted. I didn't even read this part. Nor do I have any comments on it. If you have a problem with it. i suggest you contact the people that wrote it. If Clintonian refers to refers to our lying crooked x pres, those are are fighting words. I never voted for the lowlife.
You pasted and posted, from the HT Marketroids. They were doing fine
until this paragraph which is Clintonian in its mixture of half truth
and fibs. I never thought you personally were responsible.

HT sacrificed all for low latency and low cost in the first couple
versions. "Network Extensions" started to fix it, and I have hopes for
HT3 when it comes out.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

[Grumble]

dannysdailys wrote: Assuming you already know the answer; what you may not know that most AMD processors are unlocked [...]

Not quite. Only the FX models are unlocked.

The other models allow lower multipliers for Cool and Quiet.

[George Macdonald]

On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:
On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote: On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote:
> Nope. As George stated, it was in opposition the "back-side <cache> bus"> of the P6. The P5 had no "FSB".>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let'ssee just how many people you can convince of that.:-) Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is only kinda-sorta a bus in itself. Really it's more of a point-to-point link, though it's in that fuzzy area that blurs the lines between the two a bit (where the GTL+ bus used in the P6 is definitely a bus and Hypertransport is definitely not a bus, EV6 falls somewhere in between).You're out to lunch here for the most part.

If you go look up some tech docs & data sheets you'll find that he's spot
on... as usual. EV6 is not a bus by the usual criteria.
While the term may have originated the way you say, it was then laterused to indicate the connection between the CPU and the chipset. Yes, a lot of people incorrectly refer to the a connection between the CPU and the chipset as a "Front Side Bus". Just because lots of people make a mistake that doesn't mean that they are right.Wrong. FSB is defined as the bus connection between the CPU and chipset.AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4.

You'll have to cite a technical reference for AMD calling the HT link to
the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer
sub-system nomenclature will not do it.
Ifyou break down the term, it's pretty simple. Front side, meaning not theback side, and bus. A bus is a collection of 1 or more electricalconnections between 2 or more points. The type of bus (standard, EV6, HTlink, or any other type) is of no concern.

If we allow a bit of slack and call the on-die L2 cache connection a BSB,
we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
all it carries the same traffic as a FSB. AMD has used this terminology
for its K7 architecture though some have argued with that. With the K8 the
HT link to to the I/O sub-system, however, there is no CPU<-> memory
traffic, which is the principal function of a FSB and is the derivation of
the name; the up/down HT link doesn't even serve the same functions as a
FSB.
People also still call the memory controller the "northbridge" and the I/O chip a "southbridge", which also makes no sense given that they are no longer being connected via PCI and they usually aren't bridges at all. Again, just because people incorrectly use a term doesn't make it correct.What? The northbridge has much more in it than just a memory controller.And the K8 northbridge doesn't even have a memory controller in it.

<cough><splutter> You just fell in.

The K8 architecture does not have a north bridge... and in the case of
nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.
Now, that sameconnection is the HT link of the K8. So it only makes sense to use thesame terminology for the very specific connection even though memorydata now has own single use bus for the memory. It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH less sense with the Athlon64/Opteron. Just because it's a common mistake doesn't make it any less of a mistake.Well, AMD and Intel disagree, as do I. ANd it's used for one purpose IMO,to distinquish which fricking bus you are talking about.

I won't argue about K7/P4/P-M but for K8.... references.
The FSB still carries all otherIO operations to/from the system. Once they move all this into the CPU,there will no longer be a FSB. Until then, a duck by any other name isstill a duck. Yes, but that still doesn't make a goose a duck, even if lots of people mix the two of them up.Just out of curiosty, I'd like you to tell me what the name of the busis between the CPU and the chipset. And I don't mean what type of bus.It's already known to be an HT link. So what's the name you want to giveit so that when someone refers to it by that name they will know exactlywhich bus you are talking about and where it connects. And it has to bespecific. Sytem bus doesn't cut, there's many system buses. CPU busdoesn't cut it as there are many cpu busses if you count the internalbusses. I say FSB. I'm waiting for a better one from you.

AMD has used the term "I/O connection" when HT connects the CPU to an I/O
chipset; before Pentium Pro it was called system bus or IIRC main bus or
even main system bus.
The point is that you can't have a "front side bus" unless you have a corresponding "back side bus". Hypertransport does not have such a corresponding back side so therefore it's not the "front side" of anything.I'll give you two options. Take your pick. (1) The internal bus to the L2cache is the back side bus. It just internal now. (2) Why must there be aBSB at all? FSB is more of a designation for a certain bus rather thanactually describing it's location. It connects between the CPU andchipset, just as it did on the Athlon (non 64) cpu's. And no one had anycomplaints of calling it a FSB then. That's what AMD called it.

Again, the most important task of a FSB has been CPU<->memory traffic - the
K8's HT doesn't do that... different topology... it's not an FSB.
Why are you stuck on the Pentium Pro. FSB has been used for years toindicate the connection between the CPU and the chipset. The term "Front Side Bus" was never used with the Pentium chips because there was only one bus. FSB came into computer use with the PentiumPro where Intel introduced a chip with a Frontside Bus (connecting to main memory and I/O) and a Backside bus (connecting to cache).How many times must you guys write this? No one argues that point.

But you just did - you asked why we were "stuck" on Pentium Pro... the
origin of the term FSB.
The terminology continued through the PII and early PIII chips, as well as early Athlon chips, as they had two buses, one for memory and I/O and the other for cache. For chips with only a single bus the term "FSB" makes no sense. Never has and never will, no matter how many people make such a mistake.It makes all the sense in the world defined as the connection between theCPU and chipset. If not, tell me what does. All you people have said it'snot right, yet none of you have come up with a definitive name for thebus. I wonder if that's why it's stuck around so long, since I've seen itdefined as just that, the bus between the CPU and chipset.

No it makes no sense at all, since by definition, as the cohort of a BSB,
it carries CPU<->memory traffic. To belabor the point: the BSB carried
CPU<->L2 Cache traffic and on cache misses, the traffic is "diverted" to
FSB.
Hypertransport is NOT an 'bus' in any way, shape or form. HT is a point-to-point link. PCI-E and AGP are also definitely not buses, though I expect many people to incorrectly call them such. PCI and ISA are busesI don't know what you think a bus is. perhaps you should give yourdefinition of a bus, and not a school bus. Every definition of bus I'veseen says it an electrical pathway. So unless the HT link works withoutelectricty, it's a bus. As are all the others you claim aren't.

You are (apparently) confused by an electrician's bus and a computer
architect's bus. To some system experts/architects -- and there is at
least one of them arguing with you -- the term "bus" implies "multi-drop
bus", as is the case with Intel's GTL+ and AGTL+. It is also often used
more loosely, as is the case of K7. When it is used with an accompanying
qualifier, like PCI Bus, USB, FSB etc. it is generally a specific
designation for something which is well, even formally, defined
functionality. In K8, HT does not fulfill the same functionality as FSB.
And now the killer punch. From;http://www.hypertransport.org/consortium/cons_faqs.cfm9. How does HyperTransport technology compare to other bus technologies?As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,HyperTransport provides a far simplier electrical interface, but with muchgreater bandwidth. Instead of a wide, address/data/control multidrop,shared bus such as implemented by PCI, PCI-X or SysAD technologies,HyperTransport deploys narrow, but very fast unidirectional links to carryboth data and command information encoded into packets. Unidirectionallinks provide significantly better signal integrity at high speeds andenable much faster data transfers with low-power 1.2V LVDS signals. Inaddition, link widths can be asymmetrical, meaning that 2 bit wide linkscan easily connect to 8 bit wide links and 8 bit wide links can connect to16 or 32 bit wide links and so on. Thus, the HyperTransport Technologyeliminates the problems associated with high speed parallel buses withtheir many noisy bus signals (multiplexed data/address, and clock andcontrol signals) while providing scalable bandwidth wherever it is neededin the system. As compared to newer serial I/O technologies such asRapidIO and PCI Express, HyperTransport shares some raw bandwidthcharacteristics, but is significantly different in some keycharacteristics.*****Read this pargraph carefully******** HyperTransport was designed to support both CPU-to-CPUcommunications as well as CPU-to-I/O transfers, thus, it features very lowlatency. Consequently, it has been incorporated into multiple x86 and MIPSarchitecture processors as an integrated front-side bus.*And don't miss this................................. ^^^^^^^^^ *Serial technologies such as PCI Express and RapidIO requireserial-deserializer interfaces and have the burden of extensive overheadin encoding parallel data into serial data, embedding clock information,re-acquiring and decoding the data stream. The parallel technology ofHyperTransport needs no serdes and clock encoding overhead making it farmore efficient in data transfers.I rest my case.;-)

What can I say?... somebody blundered... it's only a FAQ and "*integrated*
front side bus" is the only place where it refers to HT as a "bus". If you
look at
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/AMD_HyperTransport_Technology_based_System_Architecture_FINAL2.pdf
on p8 you'll find "Replacing what has traditionally been the system
'front-side bus' with a HyperTransport technology-based I/O connection
dramatically extends processor to system communication bandwidth from
2.1GB/s up to 6.4GB/s". There are pictures for you of the old FSB
architecture and the new HT-based architecture. Then on p9:
"HyperTransport technology provides a high-speed, chip-to-chip
interconnect..."

--
Rgds, George Macdonald

[Wes Newell]

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald wrote:
On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote:You're out to lunch here for the most part. If you go look up some tech docs & data sheets you'll find that he's spot on... as usual. EV6 is not a bus by the usual criteria.
Suggest you read this. One of thousands that claim it's a bus.

http://www.free-definition.com/Front-side-bus.html
Wrong. FSB is defined as the bus connection between the CPU and chipset.AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4. You'll have to cite a technical reference for AMD calling the HT link to the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer sub-system nomenclature will not do it.
I'm not wasting any more time citing crap for you. The proof is down
below, which you tend to ignore.
Ifyou break down the term, it's pretty simple. Front side, meaning not theback side, and bus. A bus is a collection of 1 or more electricalconnections between 2 or more points. The type of bus (standard, EV6, HTlink, or any other type) is of no concern. If we allow a bit of slack and call the on-die L2 cache connection a BSB, we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after all it carries the same traffic as a FSB. AMD has used this terminology for its K7 architecture though some have argued with that. With the K8 the HT link to to the I/O sub-system, however, there is no CPU<-> memory traffic, which is the principal function of a FSB and is the derivation of the name; the up/down HT link doesn't even serve the same functions as a FSB.
The cpu to system memory function was just one of many functions the FSB
does. it still has cpu to memory functions and feeds data to/from the
memory on the video card, the cache memory on each hard drive, memory on
other cards, etc, etc, etc.
What? The northbridge has much more in it than just a memory controller.And the K8 northbridge doesn't even have a memory controller in it. <cough><splutter> You just fell in.
I meant the chipset northbridge.
The K8 architecture does not have a north bridge... and in the case of nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.Well, AMD and Intel disagree, as do I. ANd it's used for one purposeIMO, to distinquish which fricking bus you are talking about. I won't argue about K7/P4/P-M but for K8.... references.
You already seen them from the Hyprtansport Consortium. Who do you want
them from before you will believe it, God? Sorry, can't help you there.
Just out of curiosty, I'd like you to tell me what the name of the busis between the CPU and the chipset. And I don't mean what type of bus.It's already known to be an HT link. So what's the name you want to giveit so that when someone refers to it by that name they will know exactlywhich bus you are talking about and where it connects. And it has to bespecific. Sytem bus doesn't cut, there's many system buses. CPU busdoesn't cut it as there are many cpu busses if you count the internalbusses. I say FSB. I'm waiting for a better one from you. AMD has used the term "I/O connection" when HT connects the CPU to an I/O chipset; before Pentium Pro it was called system bus or IIRC main bus or even main system bus.
So, I'm supposed to tell someone that the CPU clockspeed is determined by
the multiplier times the I/O connection speed. Right.:-) Would you care to
guess how many I/O connections there are in a basic PC system, 100,
1000, more than that?:-)
I'll give you two options. Take your pick. (1) The internal bus to theL2 cache is the back side bus. It just internal now. (2) Why must therebe a BSB at all? FSB is more of a designation for a certain bus ratherthan actually describing it's location. It connects between the CPU andchipset, just as it did on the Athlon (non 64) cpu's. And no one had anycomplaints of calling it a FSB then. That's what AMD called it. Again, the most important task of a FSB has been CPU<->memory traffic - the K8's HT doesn't do that... different topology... it's not an FSB.
Actually you can get a functioning system without external ssytem memory.
I'd sure like to see you use a system without a video output, or a storage
device, or any of the other functions that go over the FSB. They have
them, but they're usually used in standalone places as embedded. So, to
me, the memory is not the most important function, but even if it was,
it's still just ONE of many.
It makes all the sense in the world defined as the connection betweenthe CPU and chipset. If not, tell me what does. All you people have saidit's not right, yet none of you have come up with a definitive name forthe bus. I wonder if that's why it's stuck around so long, since I'veseen it defined as just that, the bus between the CPU and chipset. No it makes no sense at all, since by definition, as the cohort of a BSB, it carries CPU<->memory traffic. To belabor the point: the BSB carried CPU<->L2 Cache traffic and on cache misses, the traffic is "diverted" to FSB.
So, if it's not a FSB because the memory bus is now seperate, then the
memory bus is the FSB. Now I'm wondering what I'm going to call my car
when I take the removable dvd player out of it. Can't call it a car
anymore can I. Lost the cigar lighter, no more car.:-)
I don't know what you think a bus is. perhaps you should give yourdefinition of a bus, and not a school bus. Every definition of bus I'veseen says it an electrical pathway. So unless the HT link works withoutelectricty, it's a bus. As are all the others you claim aren't. You are (apparently) confused by an electrician's bus and a computer architect's bus. To some system experts/architects -- and there is at least one of them arguing with you -- the term "bus" implies "multi-drop bus", as is the case with Intel's GTL+ and AGTL+. It is also often used more loosely, as is the case of K7. When it is used with an accompanying qualifier, like PCI Bus, USB, FSB etc. it is generally a specific designation for something which is well, even formally, defined functionality. In K8, HT does not fulfill the same functionality as FSB.

And there's at least one system expert/architect that disagrees with
yours, namely me. Oh, and the HT people also disagree with your expert
also. But what do they know, they just develope it.And now the killer punch. From;http://www.hypertransport.org/consortium/cons_faqs.cfm9. How does HyperTransport technology compare to other bus technologies?*****Read this pargraph carefully******** HyperTransport was designed to support both CPU-to-CPUcommunications as well as CPU-to-I/O transfers, thus, it features verylow latency. Consequently, it has been incorporated into multiple x86and MIPS architecture processors as an integrated front-side bus. *Anddon't miss this................................. ^^^^^^^^^ *I rest my case.;-) What can I say?... somebody blundered... it's only a FAQ and

No kidding, and it was you.
"*integrated* front side bus" is the only place where it refers to HT as a "bus".

Well, if it's a bus in one place, what is it in another? A motorcycle
maybe. Hmmm... it connects to the cpu and chipset just like other buses
did, so that means it can't be a bus.:-)
If you look at http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/AMD_HyperTransport_Technology_based_System_Architecture_FINAL2.pdf on p8 you'll find "Replacing what has traditionally been the system 'front-side bus' with a HyperTransport technology-based I/O connection dramatically extends processor to system communication bandwidth from 2.1GB/s up to 6.4GB/s". There are pictures for you of the old FSB architecture and the new HT-based architecture. Then on p9: "HyperTransport technology provides a high-speed, chip-to-chip interconnect..."

Sorry, my K8 system isn't designed the same way as it is in the diagram
you reference, and I doubt yours is either. Look at it closely. look at
the northbridge, and then look at the other side. What's changed other
than the name? One thing, the memory bus moved to the cpu. Now look at the
southbridge and then the other side. What's cahnged other than the name?
NOTHING. the chipset makers didn't adhere to these name changes either.
I've got a nortbridge and southbrige chipset, and there isn't any HT link
between them on my system. Basically, all they are saying is they replaced
the traditional (for AMD) EV6 FSB with an HT Link FSB. Although they do
show it going from the north to the southbridge, which isn't the case with
most chipsets. If you want to see the architecture of your chipset go to
their website. Mine uses multitol between the two. VIA uses something
else, and I'm sure each has their own bus type between the 2 devices.

Let's see. I've proven the HT link can be a bus. I've proven the HT link
is a FSB when connected betwen the cpu and chipset. That's it for me. if
you need proof from someone other than the people that develope HT
technology you'll have to get it elsewhere. Although if Ford tells me they
build cars, and someone else tells me they don't. I think I'd have to
believe Ford.

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[Tony Hill]

On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote: People also still call the memory controller the "northbridge" and the I/O chip a "southbridge", which also makes no sense given that they are no longer being connected via PCI and they usually aren't bridges at all. Again, just because people incorrectly use a term doesn't make it correct.What? The northbridge has much more in it than just a memory controller.And the K8 northbridge doesn't even have a memory controller in it.

It's also not a bridge nor is it 'north' (or 'south') of anything.
The term "northbridge" and "southbridge" come specifically from
definitions of PCI bridges. None of today's chipsets use PCI to
interconnect their two (or more) ICs that make up their motherboards
chipsets.
Yes, but that still doesn't make a goose a duck, even if lots of people mix the two of them up.Just out of curiosty, I'd like you to tell me what the name of the busis between the CPU and the chipset.

Typically I refer to it exactly as it is: "CPU to chipset bus".
Hypertransport is NOT an 'bus' in any way, shape or form. HT is a point-to-point link. PCI-E and AGP are also definitely not buses, though I expect many people to incorrectly call them such. PCI and ISA are busesI don't know what you think a bus is. perhaps you should give yourdefinition of a bus, and not a school bus. Every definition of bus I'veseen says it an electrical pathway. So unless the HT link works withoutelectricty, it's a bus. As are all the others you claim aren't.And now the killer punch. From;http://www.hypertransport.org/consortium/cons_faqs.cfm9. How does HyperTransport technology compare to other bus technologies?As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,HyperTransport provides a far simplier electrical interface, but with muchgreater bandwidth. Instead of a wide, address/data/control multidrop,shared bus such as implemented by PCI, PCI-X or SysAD technologies,HyperTransport deploys narrow, but very fast unidirectional links to carryboth data and command information encoded into packets. Unidirectionallinks provide significantly better signal integrity at high speeds andenable much faster data transfers with low-power 1.2V LVDS signals. Inaddition, link widths can be asymmetrical, meaning that 2 bit wide linkscan easily connect to 8 bit wide links and 8 bit wide links can connect to16 or 32 bit wide links and so on. Thus, the HyperTransport Technologyeliminates the problems associated with high speed parallel buses withtheir many noisy bus signals (multiplexed data/address, and clock andcontrol signals) while providing scalable bandwidth wherever it is neededin the system. As compared to newer serial I/O technologies such asRapidIO and PCI Express, HyperTransport shares some raw bandwidthcharacteristics, but is significantly different in some keycharacteristics.*****Read this pargraph carefully********

Err, and where exactly does it say that this is a bus? It says that
it REPLACES buses. From your link above:

<quoting>

7. What is HyperTransport technology?

HyperTransport chip-to-chip interconnect technology is a highly
optimized, high performance and low latency board-level architecture
for embedded and open- architecture systems. It provides up to 22.4
Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth in a
highly efficient chip-to-chip technology that replaces existing
complex multi-level buses.

<end quote>


"I/O Link", "chip-to-chip interconnect" and "chip-to-chip technology"
are all used to describe it. Not "bus" because it isn't a bus.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[Tony Hill]

On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:
On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote: On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote: Not true at all. The original AMD Athlon had both a front-side bus, connecting the CPU to the chipset, I/O and memory, and a backside bus that connected the CPU to the cache chips on the Slot-A cartridge. This was actually the last x86 CPU that I'm aware of which did have a frontside bus (Intel had already gone to integrated cache by this time).Just because the cache is integrated doesn't mean the cache isn't on the"back side" of the processor. The "back-side" concept was really aseparation of the cache from the memory busses.

Ok, I'll grant that point. I would still say that it's not really an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[keith]

On Sat, 10 Sep 2005 02:43:11 +0000, Wes Newell wrote:
On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald wrote: On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote:You're out to lunch here for the most part. If you go look up some tech docs & data sheets you'll find that he's spot on... as usual. EV6 is not a bus by the usual criteria. Suggest you read this. One of thousands that claim it's a bus.

I suggest you understand what a bus is, and forget what the popular press
says.
http://www.free-definition.com/Front-side-bus.html

Yawn.
Wrong. FSB is defined as the bus connection between the CPU andchipset. AMD calls the bus a FSB and I'm pretty sure Intel did too onthe P4. You'll have to cite a technical reference for AMD calling the HT link to the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer sub-system nomenclature will not do it. I'm not wasting any more time citing crap for you. The proof is down below, which you tend to ignore.

There is no such "proof". The definition of a "bus" is much older than
even you. A buss is a multi-drop utility. ...kinda like what you take to
work. A point-to-point facility is never referred to as a "bus".
Ifyou break down the term, it's pretty simple. Front side, meaning notthe back side, and bus. A bus is a collection of 1 or more electricalconnections between 2 or more points. The type of bus (standard, EV6,HT link, or any other type) is of no concern. If we allow a bit of slack and call the on-die L2 cache connection a BSB, we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after all it carries the same traffic as a FSB. AMD has used this terminology for its K7 architecture though some have argued with that. With the K8 the HT link to to the I/O sub-system, however, there is no CPU<-> memory traffic, which is the principal function of a FSB and is the derivation of the name; the up/down HT link doesn't even serve the same functions as a FSB. The cpu to system memory function was just one of many functions the FSB does.

Nope. As you've been told a hundred times now, the FSB was so named
because Intel broke off the L2 cache from the system bus, and named the
cache interface the "back-side bus", this the memory and I/O bus became
the "front side". Those descriptions no longer fit the K8 system
architecture, so are discarded. ...no matter what the nitwits in the
popular press say.
it still has cpu to memory functions and feeds data to/from the memory on the video card,

That's an I/O function.
the cache memory on each hard drive

You really are stretching things thin.
memory on other cards, etc, etc, etc.

What cards? Memory mapped I/O? PLease! That's still I/O.
What? The northbridge has much more in it than just a memorycontroller. And the K8 northbridge doesn't even have a memorycontroller in it. <cough><splutter> You just fell in. I meant the chipset northbridge.

You fell in again.
The K8 architecture does not have a north bridge... and in the case of nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.Well, AMD and Intel disagree, as do I. ANd it's used for one purposeIMO, to distinquish which fricking bus you are talking about. I won't argue about K7/P4/P-M but for K8.... references. You already seen them from the Hyprtansport Consortium. Who do you want them from before you will believe it, God? Sorry, can't help you there.

You're the one who needs help! ...lots of it!
Just out of curiosty, I'd like you to tell me what the name of the busis between the CPU and the chipset. And I don't mean what type of bus.It's already known to be an HT link. So what's the name you want togive it so that when someone refers to it by that name they will knowexactly which bus you are talking about and where it connects. And ithas to be specific. Sytem bus doesn't cut, there's many system buses.CPU bus doesn't cut it as there are many cpu busses if you count theinternal busses. I say FSB. I'm waiting for a better one from you. AMD has used the term "I/O connection" when HT connects the CPU to an I/O chipset; before Pentium Pro it was called system bus or IIRC main bus or even main system bus. So, I'm supposed to tell someone that the CPU clockspeed is determined by the multiplier times the I/O connection speed. Right.:-) Would you care to guess how many I/O connections there are in a basic PC system, 100, 1000, more than that?:-)

Depending on the architecture... But to say it's a FSB is simply *WRONG*.
I'll give you two options. Take your pick. (1) The internal bus to theL2 cache is the back side bus. It just internal now. (2) Why must therebe a BSB at all? FSB is more of a designation for a certain bus ratherthan actually describing it's location. It connects between the CPU andchipset, just as it did on the Athlon (non 64) cpu's. And no one hadany complaints of calling it a FSB then. That's what AMD called it. Again, the most important task of a FSB has been CPU<->memory traffic - the K8's HT doesn't do that... different topology... it's not an FSB. Actually you can get a functioning system without external ssytem memory.

I'd like to see that! BIOS won't post without system memory. BEEEEP!
I'd sure like to see you use a system without a video output, or a storage device, or any of the other functions that go over the FSB.

No problem. Many servers have no video cards, keyboards, nor mice.
Storage devices are optional too (thin clients anyone), but memory isn't.
....not sure what your point is though (you have none; you loose).
They have them, but they're usually used in standalone places as embedded. So, to me, the memory is not the most important function, but even if it was, it's still just ONE of many.

Really? Without memory nothing works. That's hardly the point though.
The micro-architecture of systems has changed; so does the terminology.
Is this *really* that hard for you to comprehend?
It makes all the sense in the world defined as the connection betweenthe CPU and chipset. If not, tell me what does. All you people havesaid it's not right, yet none of you have come up with a definitivename for the bus. I wonder if that's why it's stuck around so long,since I've seen it defined as just that, the bus between the CPU andchipset. No it makes no sense at all, since by definition, as the cohort of a BSB, it carries CPU<->memory traffic. To belabor the point: the BSB carried CPU<->L2 Cache traffic and on cache misses, the traffic is "diverted" to FSB. So, if it's not a FSB because the memory bus is now seperate, then the memory bus is the FSB.

No, the FSB was named such because it was *not* the back-side cache bus.
Now I'm wondering what I'm going to call my car when I take the removable dvd player out of it. Can't call it a car anymore can I. Lost the cigar lighter, no more car.:-)

My guess is that you are as stupid as you make yourself out to be. Go
figure.
I don't know what you think a bus is. perhaps you should give yourdefinition of a bus, and not a school bus. Every definition of bus I'veseen says it an electrical pathway. So unless the HT link works withoutelectricty, it's a bus. As are all the others you claim aren't. You are (apparently) confused by an electrician's bus and a computer architect's bus. To some system experts/architects -- and there is at least one of them arguing with you -- the term "bus" implies "multi-drop bus", as is the case with Intel's GTL+ and AGTL+. It is also often used more loosely, as is the case of K7. When it is used with an accompanying qualifier, like PCI Bus, USB, FSB etc. it is generally a specific designation for something which is well, even formally, defined functionality. In K8, HT does not fulfill the same functionality as FSB. And there's at least one system expert/architect that disagrees with yours, namely me. Oh, and the HT people also disagree with your expert also. But what do they know, they just develope it.

Oh, and what would your credentials be to call yourself a system "expert"
or *architect*? You've certainly shown no such expertice here! The HT
architects certainly do *not* call the HT a bus, nor a front-side
*anything*.

<snip - bedtime; zzzzzzz>

--
Keith

[Wes Newell]

On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:
<w.newell@TAKEOUTverizon.net> wrote:And now the killer punch. From;http://www.hypertransport.org/consortium/cons_faqs.cfm9. How does HyperTransport technology compare to other bus technologies?As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,HyperTransport provides a far simplier electrical interface, but with muchgreater bandwidth. Instead of a wide, address/data/control multidrop,shared bus such as implemented by PCI, PCI-X or SysAD technologies,HyperTransport deploys narrow, but very fast unidirectional links to carryboth data and command information encoded into packets. Unidirectionallinks provide significantly better signal integrity at high speeds andenable much faster data transfers with low-power 1.2V LVDS signals. Inaddition, link widths can be asymmetrical, meaning that 2 bit wide linkscan easily connect to 8 bit wide links and 8 bit wide links can connect to16 or 32 bit wide links and so on. Thus, the HyperTransport Technologyeliminates the problems associated with high speed parallel buses withtheir many noisy bus signals (multiplexed data/address, and clock andcontrol signals) while providing scalable bandwidth wherever it is neededin the system. As compared to newer serial I/O technologies such asRapidIO and PCI Express, HyperTransport shares some raw bandwidthcharacteristics, but is significantly different in some keycharacteristics.*****Read this pargraph carefully******** Err, and where exactly does it say that this is a bus? It says that it REPLACES buses. From your link above:
You know where it said it. In the pararagraph that you cut out.:-)
<quoting> 7. What is HyperTransport technology? HyperTransport chip-to-chip interconnect technology is a highly optimized, high performance and low latency board-level architecture for embedded and open- architecture systems. It provides up to 22.4 Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth in a highly efficient chip-to-chip technology that replaces existing complex multi-level buses. <end quote> "I/O Link", "chip-to-chip interconnect" and "chip-to-chip technology" are all used to describe it. Not "bus" because it isn't a bus.
It calls it a bus (a Front Side bus at that) in the portion you snipped
out and you know it. I don't know why you cut it out. it only makes you
look trollish. Here's some more info for you.

http://www.free-definition.com/Front-side-bus.html

http://www.free-definition.com/category/Computer_bus

--
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Need good help? Provide all system info with question.
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[Wes Newell]

On Fri, 09 Sep 2005 23:18:00 -0400, keith wrote:
On Sat, 10 Sep 2005 02:43:11 +0000, Wes Newell wrote: Suggest you read this. One of thousands that claim it's a bus. I suggest you understand what a bus is, and forget what the popular press says. http://www.free-definition.com/Front-side-bus.html Yawn.
Typical response from someone that has no valid arguement.
I'm not wasting any more time citing crap for you. The proof is down below, which you tend to ignore. There is no such "proof". The definition of a "bus" is much older than even you. A buss is a multi-drop utility. ...kinda like what you take to work. A point-to-point facility is never referred to as a "bus".
You wouldn't know the definition if it bit you on the ass. But, just to
show how stupid this response is, the frontside bus was point to point, as
was the back side bus. The same could be said for the memory bus. IOW's
you don't know wtf you are talking about.
The cpu to system memory function was just one of many functions the FSB does. Nope. As you've been told a hundred times now, the FSB was so named because Intel broke off the L2 cache from the system bus, and named the cache interface the "back-side bus", this the memory and I/O bus became the "front side". Those descriptions no longer fit the K8 system architecture, so are discarded. ...no matter what the nitwits in the popular press say.
What makes you think you have to keep repeating how the FSB name came
about. I think everyone that's been following this thread already knows
that. And the original description still fits, with an additional memory
bus. But wait, can that be called a bus by your "definition".:-)
it still has cpu to memory functions and feeds data to/from the memory on the video card, That's an I/O function.
And wtf do you call reads and writes to system memory, a fricking crystal
ball. You've dug yourself a hole so deep it appears you don't even know
what I/O is.
the cache memory on each hard drive You really are stretching things thin.
No, I just don't turn a blind eye to facts.
memory on other cards, etc, etc, etc. What cards? Memory mapped I/O? PLease! That's still I/O.
Christ, everything from the CPU is I/O. That's what they do, take Input,
give Output.:-)
>What? The northbridge has much more in it than just a
memory>controller. And the K8 northbridge doesn't even have a memory>controller in it. <cough><splutter> You just fell in. I meant the chipset northbridge. You fell in again.
Yep. I screwed up there. At least I can admit it.
You already seen them from the Hyprtansport Consortium. Who do you want them from before you will believe it, God? Sorry, can't help you there. You're the one who needs help! ...lots of it!
I think others will know who really needs the help.
So, I'm supposed to tell someone that the CPU clockspeed is determined by the multiplier times the I/O connection speed. Right.:-) Would you care to guess how many I/O connections there are in a basic PC system, 100, 1000, more than that?:-) Depending on the architecture... But to say it's a FSB is simply *WRONG*.
Then tell the Hypertransport consortium, not me. Although I do agree with
them.
Actually you can get a functioning system without external ssytem memory. I'd like to see that! BIOS won't post without system memory. BEEEEP!
Are you really this nearsighted. I do believe there are already single
chip proceessors on teh market that have the system memory on the cpu die.
If not, there will be. It's easy to do. I wasn't refering specifically to
current x86 systems. I'd sure like to see you use a system without a video output, or a storage device, or any of the other functions that go over the FSB. No problem. Many servers have no video cards, keyboards, nor mice.

Not without a FSB. Even the lowly old serial data goes thru it. IOW's
there's no way to communicate with the cpu without it. I thought I put
that simple enough for even the most simpleminded people on earth to see.
I guess not.
Storage devices are optional too (thin clients anyone), but memory isn't. ...not sure what your point is though (you have none; you loose).
Think a little deeper.:-)
They have them, but they're usually used in standalone places as embedded. So, to me, the memory is not the most important function, but even if it was, it's still just ONE of many. Really? Without memory nothing works.

I said external system memory. i guess you need some remedial reading help
too. That's hardly the point though. The micro-architecture of systems has changed; so does the terminology. Is this *really* that hard for you to comprehend?
It seems your the one having trouble comprehending.:-)
So, if it's not a FSB because the memory bus is now seperate, then the memory bus is the FSB. No, the FSB was named such because it was *not* the back-side cache bus.
ROFLMAO. Did you actually read what you typed.:-)
Now I'm wondering what I'm going to call my car when I take the removable dvd player out of it. Can't call it a car anymore can I. Lost the cigar lighter, no more car.:-) My guess is that you are as stupid as you make yourself out to be. Go figure.
Your post are funny. I'll give you that much. Totally fubar, but funny.
And there's at least one system expert/architect that disagrees with yours, namely me. Oh, and the HT people also disagree with your expert also. But what do they know, they just develope it. Oh, and what would your credentials be to call yourself a system "expert" or *architect*? You've certainly shown no such expertice here! The HT architects certainly do *not* call the HT a bus, nor a front-side *anything*.
Sure they do/did. You already seen it, but chosen to ignore it. I'll quote
it qagain just for you now that I know you're a little slow. it's even
implied in the question. Otherwise, the word 'other' would not be there.
it would simply be 'to bus technologies'.

9. How does HyperTransport technology compare to other bus technologies?

*this is the relevent part*
HyperTransport was designed to support both CPU-to-CPU communications as
well as CPU-to-I/O transfers, thus, it features very low latency.
Consequently, it has been incorporated into multiple x86 and MIPS
architecture processors as an integrated front-side bus.

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[keith]

On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:
On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote: On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net> wrote: Not true at all. The original