Comparison across Pentium CPU generations

[P2B]

I happened to have a pair of PII 400 Slot-1 processors and a pair of
PIII-S engineering samples on slot adapters on hand - the former
designed to run at 4 x 100Mhz and the latter capable of doing so.

For interest's sake I ran a bunch of benchmarks, at 4 x 100, which say
the Tualatin is on average almost 20% faster than the PII at the same
clock speeds on the same motherboard in both single and dual processor
configurations.

Is the difference all due to the Tualatin's full speed vs. the PII's
half speed L2 cache, or are other factors at play?

[scott]

cache size?

"P2B" <p2b@sympatico.ca> wrote in message
news:QSvIb.8331$Vl6.1770104@news20.bellglobal.com... I happened to have a pair of PII 400 Slot-1 processors and a pair of PIII-S engineering samples on slot adapters on hand - the former designed to run at 4 x 100Mhz and the latter capable of doing so. For interest's sake I ran a bunch of benchmarks, at 4 x 100, which say the Tualatin is on average almost 20% faster than the PII at the same clock speeds on the same motherboard in both single and dual processor configurations. Is the difference all due to the Tualatin's full speed vs. the PII's half speed L2 cache, or are other factors at play?

[Tony Hill]

On Wed, 31 Dec 2003 03:36:10 -0500, P2B <p2b@sympatico.ca> wrote:I happened to have a pair of PII 400 Slot-1 processors and a pair ofPIII-S engineering samples on slot adapters on hand - the formerdesigned to run at 4 x 100Mhz and the latter capable of doing so.For interest's sake I ran a bunch of benchmarks, at 4 x 100, which saythe Tualatin is on average almost 20% faster than the PII at the sameclock speeds on the same motherboard in both single and dual processorconfigurations.Is the difference all due to the Tualatin's full speed vs. the PII'shalf speed L2 cache, or are other factors at play?

That's the main difference between the two. Tualatin's cache is not
only much faster (400MHz vs. 200MHz in this case), it also has
significantly lower latency (probably about 10-15 clock cycles vs.
40-50) and much higher bandwidth than the cache clock speed would
indicate (Tualatin uses a 256-bit wide bus for L2 cache vs. 64-bit for
the PII). So the Tualatin actually has 8 times as much cache
bandwidth as the old PIII. Also, when running a dual-processor
configuration, cache is doubly important since you have a shared bus
to main memory.

There are also a few other little points of interest. Tualatin, being
a PIII processor, of course supports SSE. That may be boosting the
performance of some applications here and there. There are also a few
little tweaks that where made here and there. Usually these changes
aren't announced much and I don't know the specifics off hand, but for
example the TLB might have been improved, or the branch predictors
might have been beefed up, or even some of the instructions might have
been speeded up here or there. Just little things here and there, but
they do add up.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

[P2B]

Tony Hill wrote:
On Wed, 31 Dec 2003 03:36:10 -0500, P2B <p2b@sympatico.ca> wrote:I happened to have a pair of PII 400 Slot-1 processors and a pair ofPIII-S engineering samples on slot adapters on hand - the formerdesigned to run at 4 x 100Mhz and the latter capable of doing so.For interest's sake I ran a bunch of benchmarks, at 4 x 100, which saythe Tualatin is on average almost 20% faster than the PII at the sameclock speeds on the same motherboard in both single and dual processorconfigurations.Is the difference all due to the Tualatin's full speed vs. the PII'shalf speed L2 cache, or are other factors at play? That's the main difference between the two. Tualatin's cache is not only much faster (400MHz vs. 200MHz in this case), it also has significantly lower latency (probably about 10-15 clock cycles vs. 40-50) and much higher bandwidth than the cache clock speed would indicate (Tualatin uses a 256-bit wide bus for L2 cache vs. 64-bit for the PII). So the Tualatin actually has 8 times as much cache bandwidth as the old PIII. Also, when running a dual-processor configuration, cache is doubly important since you have a shared bus to main memory.

That would explain it - while memtest86 doesn't report the Tualatin's L2
cache as 8x faster, it's a lot more than double, 1781MB/s vs. 529MB/s.
Memtest says the L1 caches are the same, 32K/3930MB/s, but curiously,
sees main memory as slightly faster with the Tualatins - 279MB/s vs.
252MB/s. I suppose one would have to know how memtest arrives at these
numbers to understand why.
There are also a few other little points of interest. Tualatin, being a PIII processor, of course supports SSE. That may be boosting the performance of some applications here and there. There are also a few little tweaks that where made here and there. Usually these changes aren't announced much and I don't know the specifics off hand, but for example the TLB might have been improved, or the branch predictors might have been beefed up, or even some of the instructions might have been speeded up here or there. Just little things here and there, but they do add up. ------------- Tony Hill hilla <underscore> 20 <at> yahoo <dot> ca

[Tony Hill]

On Wed, 31 Dec 2003 13:05:49 -0500, P2B <p2b@sympatico.ca> wrote: That's the main difference between the two. Tualatin's cache is not only much faster (400MHz vs. 200MHz in this case), it also has significantly lower latency (probably about 10-15 clock cycles vs. 40-50) and much higher bandwidth than the cache clock speed would indicate (Tualatin uses a 256-bit wide bus for L2 cache vs. 64-bit for the PII). So the Tualatin actually has 8 times as much cache bandwidth as the old PIII. Also, when running a dual-processor configuration, cache is doubly important since you have a shared bus to main memory.That would explain it - while memtest86 doesn't report the Tualatin's L2cache as 8x faster, it's a lot more than double, 1781MB/s vs. 529MB/s.

Actually I think my memory might be a bit fuzzy about the exact speed
of the L2 cache for the Tualatins and the above just jarred something
from the fog. I think that the Tualatins do indeed have a 256-bit
wide cache running at full processor speed, but that they only send
data on every second clock cycle, resulting in only a 4x increase in
cache data throughput. This is close to the speeds that your seeing.

I know that this is how the cache on the "Coppermine" PIIIs worked,
while on the P4's the cache is 256-bits wide but sends data on every
clock cycle (like I described in my first post). I really can't
remember where the Tualatins fit into this though.
Memtest says the L1 caches are the same, 32K/3930MB/s, but curiously,sees main memory as slightly faster with the Tualatins - 279MB/s vs.252MB/s. I suppose one would have to know how memtest arrives at thesenumbers to understand why.

Tualatin may have data prefetching in hardware, though again my memory
is a touch fuzzy on this point. It definitely supports software
prefetching through SSE, though I'm pretty certain that Memtest86
doesn't make use of this. Again, I can't remember just at what stage
this feature was added, but hardware data prefetching could explain
the different numbers you're seeing.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca