I learned in my basic digital logic and design courses that the clock rate
determined the rate at which flip-flops/registers could read in data. My
question is how can a GPU running at say, 500Mhz, clock-in AGP data at a
rate of 2+GB/sec? I suppose if the registers clock in data on the rising and
falling edges it wouldn't be an issue. Is this what happens?
On Tue, 03 Oct 2006 06:26:42 GMT "pigdos" <NA@nowhere.com> wrote in
Message id: <ConUg.12593$7I1.5528@newssvr27.news.prodigy.net>:
Quote:
I learned in my basic digital logic and design courses that the clock ratedetermined the rate at which flip-flops/registers could read in data. Myquestion is how can a GPU running at say, 500Mhz, clock-in AGP data at arate of 2+GB/sec? I suppose if the registers clock in data on the rising andfalling edges it wouldn't be an issue. Is this what happens?
You're assuming that the bus width is 8 bits/ 1 byte.
On Tue, 03 Oct 2006 06:26:42 GMT, "pigdos" <NA@nowhere.com> wrote:
Quote:
I learned in my basic digital logic and design courses that the clock ratedetermined the rate at which flip-flops/registers could read in data. Myquestion is how can a GPU running at say, 500Mhz, clock-in AGP data at arate of 2+GB/sec? I suppose if the registers clock in data on the rising andfalling edges it wouldn't be an issue. Is this what happens?
Hmm AGP bus is 32bit. So 500Mhz x 32 bit at single data rate is just
nice 2GB/sec. pPp
--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself
The little lost angel <a?n?g?e?l@lovergirl.lrigrevol.moc.com> wrote in part:
Quote:
On Tue, 03 Oct 2006 06:26:42 GMT, "pigdos" <NA@nowhere.com> wrote:
Quote:
I learned in my basic digital logic and design courses that theclock rate determined the rate at which flip-flops/registerscould read in data. My question is how can a GPU running at say,500Mhz, clock-in AGP data at a rate of 2+GB/sec? I suppose ifthe registers clock in data on the rising and falling edges itwouldn't be an issue. Is this what happens?
Hmm AGP bus is 32bit. So 500Mhz x 32 bit at single data rate is just nice 2GB/sec. pPp
True enough, but actually there's more headroom: IIRC, plain
AGP is 64bit * 66 MHz = 528 MB/s [peak, outside of longish setup]
AGP does go to 8x = 4.2 GB/s bus limit. If GPU is 64+bit, then
500 MHz GPU limit is 4.0 GB/s, assuming one clock per xfr.
The GPU's bus is mostly busy hammering on vid.ram. DMA [busmaster]
transfer to system RAM are usually infrequent, which is one reason
why plain PCI vid.cards are sold (The other reason is for expansion
of PCIe- & AGP-less econoboxes). When transfer between system &
vid.RAM _is_ important (software MPEG2 decoding or other attempts
to use the CPU for GPU work), then systems often cannot keep up.
On Tue, 03 Oct 2006 12:48:50 GMT, Robert Redelmeier
<redelm@ev1.net.invalid> wrote:
Quote:
The little lost angel <a?n?g?e?l@lovergirl.lrigrevol.moc.com> wrote in part:
Quote:
On Tue, 03 Oct 2006 06:26:42 GMT, "pigdos" <NA@nowhere.com> wrote:
Quote:
I learned in my basic digital logic and design courses that theclock rate determined the rate at which flip-flops/registerscould read in data. My question is how can a GPU running at say,500Mhz, clock-in AGP data at a rate of 2+GB/sec? I suppose ifthe registers clock in data on the rising and falling edges itwouldn't be an issue. Is this what happens?
Hmm AGP bus is 32bit. So 500Mhz x 32 bit at single data rate is just nice 2GB/sec. pPp
True enough, but actually there's more headroom: IIRC, plainAGP is 64bit * 66 MHz = 528 MB/s [peak, outside of longish setup]AGP does go to 8x = 4.2 GB/s bus limit. If GPU is 64+bit, then500 MHz GPU limit is 4.0 GB/s, assuming one clock per xfr.
I think you're thinking of PCI-X. AGP is 32-bits address & data + 8-bits
SBA. For AGP 3.x 8x, the common clock is 66MHz, the source synchronous
strobe clocks are 4x that with DDR giving 533MT/s for a peak bandwidth for
AGP 8x of 2.1GB/s.
I see. So obviously any modern GPU can more than keep up w/AGP. Is this one
reason PCI express is the superior tech?
--
Doug
"Trent" <none@dev.nul.pissoff> wrote in message
news:dcb4i2peajjqpp2u5lcdj212nhpvf3ehan@4ax.com...
Quote:
On Tue, 03 Oct 2006 06:26:42 GMT "pigdos" <NA@nowhere.com> wrote in Message id: <ConUg.12593$7I1.5528@newssvr27.news.prodigy.net>:
Quote:
I learned in my basic digital logic and design courses that the clock ratedetermined the rate at which flip-flops/registers could read in data. Myquestion is how can a GPU running at say, 500Mhz, clock-in AGP data at arate of 2+GB/sec? I suppose if the registers clock in data on the risingandfalling edges it wouldn't be an issue. Is this what happens?
You're assuming that the bus width is 8 bits/ 1 byte.
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